A wiring substrate such as an interposer electrically connects a semiconductor chip to a semiconductor package substrate or electrically connects semiconductor chips to each other (refer to Japanese Laid-Open Patent Publication Nos. 2014-110390 and 2013-214579). Such a wiring substrate has, for example, one surface including a connection terminal connected to a semiconductor chip and another surface including a connection terminal connected to a package substrate. In the wiring substrate, wiring layers, which electrically connect the two connection terminals, and interlayer insulation layers are alternately stacked.
The scale of semiconductor chip integration has resulted in the demand for thinner wiring substrates and higher wiring pattern density. A thin wiring substrate has been developed to meet such demands. Such a thin wiring substrate may be obtained by forming an interlayer insulation layer with a thin film of a photosensitive resin such as a polyimide resin and omitting a core substrate (support member), which has high rigidity and is thicker than the interlayer insulation layer.